1. Field of the Invention
The present invention relates to a solid state imaging device having a hole accumulated diode, a method of manufacturing the same, and an imaging apparatus.
2. Description of the Related Art
Solid state imaging devices, such as a CCD (charge coupled device) and a CMOS image sensor, are widely used in a video camera, a digital still camera, and the like. Improvement in sensitivity and noise reduction are important issues in all kinds of solid state imaging devices.
In particular, a dark current, which is detected as a very small current when an electric charge (electron) generated from a minute defect in a substrate interface of a light receiving surface is input as a signal, or a dark current generated due to the interface state on the interface between a sensor section and an upper layer even though there is no pure signal charge generated by photoelectric conversion of incident light in a state where there is no incident light is a noise to be reduced in the solid state imaging device.
As a technique of suppressing generation of a dark current caused by the interface state, for example, an embed type photodiode structure having a hole accumulation layer 23 formed of a P+ layer on a sensor section (for example, a photodiode) 12 is used as shown in FIG. 9B. Moreover, in this specification, the embed type photodiode structure is referred to as an HAD (hole accumulated diode) structure. As shown in FIG. 9A, in a structure where the HAD structure is not provided, electrons generated due to the interface state flow to the photodiode as a dark current. On the other hand, as shown in FIG. 9B, in the HAD structure, generation of electrons from the interface is suppressed by the hole accumulation layer 23 formed on the interface. In addition, even if electric charges (electrons) are generated from the interface, the electric charges (electrons) do not flow to a charge accumulation section, which is a potential well in an N+ layer of the sensor section 12, but flow to the hole accumulation layer 23 of the P+ layer in which many holes exist. Accordingly, the electric charges (electrons) can be eliminated. As a result, since it can be prevented that the electric charges generated due to the interface are detected as a dark current, the dark current caused by the interface state can be suppressed.
A method of suppressing the dark current may be adopted in both a CCD and a CMOS image sensor and may also be adopted to not only a known top-emission-type image sensor but also a back illuminated image sensor (for example, refer to JP-A-2003-338615).
As a method of forming the HAD structure, it is common to perform ion implantation of impurities for forming the P+ layer, for example, boron (B) or boron difluoride (BF2) through a thermally oxidized silicon layer or a CVD oxide silicon layer formed on a substrate, to activate injected impurities by annealing, and then to form a p-type region near the interface. However, heat treatment in a high temperature of 700° C. or more is essential in order to activate doped impurities. Accordingly, formation of the hole accumulation layer using ion implantation is difficult in a low-temperature process at 400° C. or less. Also in the case of desiring to avoid long-time activation at high temperature in order to suppress diffusion of dopant, the method of forming a hole accumulation layer in which ion implantation and annealing are performed is not preferable.
Furthermore, when a silicon oxide or a silicon nitride formed on an upper layer of the sensor section is formed in a low-temperature plasma CVD method, for example, the interface state is reduced compared with an interface between of a light receiving surface and a layer formed at high temperature. The reduction in interface state increases a dark current.
As described above, in the case of desiring to avoid ion implantation and annealing process at high temperature, not only the hole accumulation layer cannot be formed by known ion implantation but also a dark current is further increased. In order to solve the problem, it becomes necessary to form a hole accumulation layer in another method that is not based on ion implantation in the related art.
As an example, there is a method of forming a layer having negative fixed electric charges on an upper layer of a sensor section. In this method, a hole accumulation layer is formed on the interface at a side of the light receiving surface of the sensor section by the electric field caused by the layer having negative fixed electric charges. Accordingly, electric charges (electrons) generated from the interface is suppressed. In addition, even if electric charges (electrons) are generated from the interface, the electric charges (electrons) do not flow to a charge accumulation portion which is a potential well in the sensor section but flow to the hole accumulation layer in which many holes exist. As a result, the electric charges (electrons) can be eliminated. Thus, since it can be prevented that a dark current generated by the electric charges on the interface is detected in the sensor section, a dark current caused by the interface state is suppressed. Thus, by using the layer having negative fixed electric charges, the HAD structure can be formed without ion implantation and annealing. The layer having negative fixed electric charges may be formed of a hafnium oxide (HfO2) layer, for example.
However, as described above, when the configuration in which the layer having negative fixed electric charges is formed on the light receiving surface is applied to a back illuminated CCD or CMOS image sensor, for example, a layer 22 having negative fixed electric charges is formed on the entire light receiving surface 12s of a sensor section 12 as shown in FIG. 10. Accordingly, a hole accumulation layer 23 (P+ layer) is formed not only in a pixel region where the HAD needs to be formed but also on a surface of a semiconductor substrate 11 on a peripheral circuit section 14.
For example, when a well region, a diffusion layer, a circuit, and the like (a diffusion layer 15 is shown as an example in the drawing) are present in the peripheral circuit section 14 so that a negative electric potential is generated on a back side of the semiconductor substrate 11, holes having positive electric charges are drawn to the negative electric potential to be diffused. Accordingly, a desired negative electric potential is not obtained due to the positive electric charges drawn but an electric potential biased toward a positive side from a designed value is output. As a result, an applied voltage of the sensor section using the electric potential is adversely affected, causing a problem that a pixel characteristic changes.